The present invention generally relates to variable digital delay lines and cascades thereof.
Delay lines--or delay cells as a synonym--are often applied in order to delay an output signal by a certain delay time with respect to an input signal. There are delay lines with a fixed delay time, and variable delay lines which allow different delay times in a predetermined range.
FIG. 1a shows a structural representation of a variable digital delay cell 5 receiving an input signal INPUT and providing an output signal OUTPUT delayed with respect to the input signal INPUT by a variable delay time t.sub.del. The value of the delay time t.sub.del, can be set by means of a control signal CTRL.
FIG. 1b depicts a structural representation of an embodiment of the variable digital delay cell 5. The input signal INPUT is applied to a first signal processing unit 10 and to a delay stage 20 with a fixed delay time T.sub.D. The delay stage 20 can be any delay circuit as known in the art such as a passive circuit, e.g. an R-C combination, or an active circuit like a buffer amplifier. An output signal of the delay stage 20 is connected to a second signal processing unit 30. Output signals of the first 10 and second 30 signal processing units are applied to a third signal processing unit 40 which combines those signals and processes therefrom the output signal OUTPUT, which is delayed with respect to the input signal INPUT by a variable delay time t.sub.del. Either the first 10 and second 30 signal processing units or the third signal processing unit 40, or all of the signal processing units, receive control signals from a control unit 50 in order to set the variable delay time t.sub.del, of the variable delay cell 5 in accordance with the applied control signal CTRL.
FIG. 1c shows as an example for the variable digital delay cell 5 embodied in ECL (emitter-coupled logic), which receives and processes differential signals. However, it is clear that the variable digital delay cell 5 can also be implemented by means of other logical elements or in a different logic such as a single line logic. The first 10 and second 30 signal processing units and the control unit 50 are embodied as current switches, and the third signal processing unit 40 is embodied as a sum up stage.
The input signal INPUT (V.sub.A) is connected to current switch 10 and to the delay stage 20 with a fixed delay time T.sub.D. An output signal V.sub.B of the delay stage 20 is connected to current switch 30. Output signals of the current switch 10 (complementary currents I.sub.AC and I.sub.AN) and of the current switch 30 (complementary currents I.sub.BC and I.sub.BN) are added by means of sum up stage 40, and the sum thereof represents the output signal OUTPUT of the variable delay cell 5.
A current I.sub.Ref is split by the control unit 50 into a current I.sub.A applied to the current switch 10 and a current I.sub.B applied to the current switch 30. By changing the ratio of the currents I.sub.A to I.sub.B, the delay time t.sub.del of the output signal OUTPUT with respect to the input signal INPUT can be varied. A minimum value t.sub.delmin of the delay time t.sub.del is achieved when I.sub.A =I.sub.Ref and I.sub.B =0, whereby t.sub.delmin will be the base delay of the variable delay cell 5 determined by the propagation delay through the current switch 10 and the sum up stage 40. A medium value t.sub.delmed can be set when I.sub.A =I.sub.Ref /2=I.sub.B, and a maximum value t.sub.delmax can be gained when I.sub.A =0 and I.sub.B =I.sub.ref. The maximum value t.sub.delmax substantially equals the fixed delay time T.sub.D of the delay stage 20 plus a propagation delay through the current switch 30 and the sum up stage 40. The ratio I.sub.A to I.sub.B can be controlled by the control signal CTRL embodied as an analog voltage.
FIG. 1d depicts signal diagrams within the circuit of FIG. 1c for an exemplary ratio I.sub.A to I.sub.B. It is to be understood that the crossing points of the differential signals, or accordingly, the medium value of the signal differences or the crossing points of the complementary currents, shall represent time marks to compare the timing of the signals. The voltage V.sub.B is delayed with respect to the voltage V.sub.A by the fixed delay time T.sub.D of the delay stage 20. The output signal OUTPUT received from the current sums (I.sub.AC +I.sub.BC) and (I.sub.AN +I.sub.BN) is delayed with respect to the input signal INPUT by the effective delay time t.sub.del.
In the circuits of FIGS. lb and 1 c, the maximum applicable delay time T.sub.D of the delay stage 20 is limited to the transition time t.sub.T (compare FIG. 1d) of output signals of the current switches 10 and 30 so that T.sub.D is selected to be T.sub.D &lt;t.sub.T. However on the other hand, the delay time t.sub.del is limited to the delay time T.sub.D, so that the delay time t.sub.del of the circuit of FIG. 1a is limited to t.sub.del .ltoreq.T.sub.D &lt;t.sub.T. A delay time t.sub.del selected to be greater than the transition time t.sub.T would cause `horizontal steps` in the output signal OUTPUT during a transition, which lead to jitter and generally are to be avoided.
In modern bipolar circuits such as ECL circuits, the base delay (as the minimum delay time t.sub.delmin) of such a delay cell 5 typically is in the range of about 50 to 100 ps, and the transition times of digital output signals typically is in the range of 100 to 200 ps. That means that the typical delay range of the delay cell 5 will be between a minimum of 50 to 100 ps and maximum of 100 to 200 ps, which leads to an applicable ratio (t.sub.delmin /t.sub.delmax) of about 1:2.
In order to provide greater values of the maximum delay time t.sub.delmax, a plurality of delay cells may be arranged in consecutive cascades. FIG. 1e shows an example of two delay cells 5, according to FIG. 1a, arranged as a cascade in a serial manner. An output signal OUT.sub.-- 1 of a first delay cell 5.1 serves as an input signal IN.sub.-- 2 of a second delay cell 5.2. Further delay cells may be arranged accordingly. However, by connecting n delay cells 5 in series, the maximum delay time t.sub.delmax may be increased n times, but the base delay, and therefore the minimum delay time t.sub.delmin, is also increased n times. That means not only that the cascade will always provide at minimum a delay time of (n.times.t.sub.delmin), but also that the ratio (t.sub.delmin /t.sub.delmax) still is 1:2.
There are several cascaded delay cells known in the art such as U.S. Pat. No. 5,210,450 disclosing a digital multiplexer-controlled delay generator that uses groups of current-switching elements to vary propagation delay in a connection input voltage to load. U.S. Pat. No. 4,797,586 discloses a high frequency signal controller delay circuit that adjusts the gain of each amplifier according to a control signal, so that at least one and not more than two amplifiers have a non-zero gain.